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copyright ? 201 2 future technology devi ces international limited 1 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 future technology devices international ltd ft2232h dual high speed usb to multipurpose uart/fifo ic the ft2232h is ftdi?s 5 th genera tion of usb devices. the ft2232h is a usb 2.0 high speed (480mb/s) to uart/fifo ic. it has the capability of being configured in a variety of industry standard serial or parallel interfaces. the ft2232h has the following advanced features: ? single chip us b to dual serial / parallel ports with a variety of configurations. ? entire usb protocol handled on the chip. no usb specific firmware programming required. ? usb 2.0 high speed (480mbits/second) and full speed (12mbits/second) compatible. ? dual multi - protocol synchronous serial engine (mpsse) to simplify synchronous serial protocol (usb to jtag, i 2 c, spi or bit - bang) design. ? dual independent uart or fifo or mpsse ports. ? independent baud rate generators. ? rs232/rs422/rs485 uart transfer data rate up to 12mbaud. (rs232 data rate limited by external level shifter). ? usb to parallel fifo transfer data rate up to 8 mbyte/sec. ? single channel synchronous fifo mode for transfers upto 40 mbytes/sec ? cpu - style fifo interface mode simplifies cpu interface design. ? mcu host bu s emulation mode configuration option. ? fast opto - isolated serial interface option. ? ftdi?s royalty ? adjustable receive buffer timeout. ? o ption for transmit and receive led drive signals on each channel. ? enhanced bit - bang mode interface option with rd# and wr # strobes ? ft245b - style fifo interface option with bi - directional data bus and simple 4 wire handshake interface. ? highly integrated des ign includes +1.8v ldo regulator for vcore, integrated por function and on chip clock multiplier pll (12mhz C ? asynchronous serial uart interface option with full hardware handshaking and modem interface signals. ? fully assisted hardware or x - on / x - off software handshaking. ? uart interface supports 7/8 bit data, 1/2 stop bits, and odd/even/mark/space/no parity. ? auto - transmit enable control for rs485 serial applications using txden pin. ? operational configuration mode and usb description strings config urable in external eeprom over the usb interface. ? configurable i/o drive strength (4, 8, 12 or 16ma) and slew rate. ? low operating and usb suspend current. ? supports bus powered, self powered and high - power bus powered usb configurations. ? uhci/ohci/ehci host controller compatible. ? usb bulk data transfer mode (512 byte packets in high speed mode). ? +1.8v (chip core) and +3.3v i/o interfacing (+5v tolerant). ? extended - 40c to 85c industrial operating temperature range. ? compact 64 - ld lead free lqfp or qfn packa ge ? +3.3v single supply operating voltage range. ? esd protection for ft2232h io?s neither the whole nor any part of the infor mation contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. this product and its documentation are supplied on an as - is basis and n o warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd will n ot accept any claim for damages
copyright ? 201 2 future technology devi ces international limited 2 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 howsoever arising as a result of use or failure of this product. your statutory right s are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in persona l injury. this document provides preliminary infor mation that may be subject to change without notice. no freedom to use patents or other intellectual property rights is impli ed by the publication of this document. future technology devices international ltd, unit 1, 2 seaward place, centurion business pa rk, glasgow g41 1hh, united kingdom. scotland registered company number: sc136640
copyright ? 201 2 future technology devi ces international limited 3 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 1 typical applications ? single chip usb to dual channel uart (rs232, rs422 or rs485). ? single chip usb to dual channel fifo. ? single chip usb to dual channel jtag. ? single chip us b to dual channel spi. ? single chip usb to dual channel i2c. ? single chip usb to dual channel bit - bang. ? single chip usb to dual combination of any of above interfaces. ? single chip usb to fast serial optic interface. ? single chip usb to cpu target interface (a s memory), double and independent. ? single chip usb to host bus emulation (as cpu). ? pda to usb data transfer ? usb smart card readers ? usb instrumentation ? usb industrial control ? usb mp3 player interface ? usb flash card reader / writers ? set top box pc - usb in terface ? usb digital camera interface ? usb bar code readers 1.1 driver support the ft2232h requires usb drivers (listed below) , available free from http://www.ftdichip.com , which are used to make the ft2232h appear as a vi rtual com port (vcp). this allows the user to communicate with the usb interface via a standard pc serial emulation port (for example tty). another ftdi usb driver, the d2xx driver, can also be used with application software to directly access the ft2232h through a dll. royalty free virtual com port (vcp) drivers for... ? windows 2000, server 2003, server 2008 ? windows xp and xp 64 - bit ? windows vista and vista 64 - bit ? windows xp embedded ? windows ce 4.2, 5.0, 5.2 and 6.0 ? mac os - x ? linux (2.6. 3 9 or later) ? windows 7 and windows 7 64 - bit royalty free d2xx direct drivers (usb drivers + dll s/w interface) ? windows 2000, server 2003, server 2008 ? windows xp and xp 64 - bit ? windows vista and vista 64 - bit ? windows xp embedded ? windows ce 4.2, 5.0, 5.2 and 6.0 ? linux (2.4 or lat er) and linux x86_64 ? windows 7 and windows 7 64 - bit for driver installation, please refer to the application note: ? an_107 , advanced driver opt ions . ? an_103, ftdi drivers installation guide for vista . ? an_119 , ftdi drivers installation guide for windows7 . ? an_104, ftdi drivers installation guide for windowsxp . the following additional installation guides application notes and technical notes are also available: ? an_113, interfacing ft2232h hi - speed devices to i2c bus . ? an_109 C programming guide for high speed ftci2c dll ? an_110 C programming guide for high speed ftcjtag dll ? an_111 C programming guide for high speed ftcspi dll ? an 113 C interfacing ft2232h hi - speed devi ces to i2c bus ? an114 C interfacing ft2232h hi - speed devices to spi bus
copyright ? 201 2 future technology devi ces international limited 4 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 ? an135 C mpsse basics ? an108 - command processor for mpsse and mcu host bus emula tion modes ? tn_104, guide to debugging customers failed driver installation 1.2 part numbers part number package ft2232hl - xxxx 64 pin lqfp ft2232hq - xxxx 64 pin qfn note: packaging code for xxxx is: - reel: taped and reel (lqfp =1000 pcs per reel, qfn =4000 pcs per reel) - tray: tray packing, (lqfp =160 pcs per tray, qfn =260 pcs per tray) pl ease refer to section 8 for all package mechanical parameters. 1.3 usb compliant the ft2232h is fully compliant with the usb 2.0 specification and has been given the usb - if test - id (tid) 40720019 . the timing of the rise/fall time of the usb signals is not onl y dependant on the usb signal drivers, it is also dependant system and is affected by factors such as pcb layout, external components and any transient protection present on the usb signals. for usb compliance these may require a slight adjustment. this t iming can be modified through a programmable setting stored in the same external eeprom that is used for the usb descriptors. timing can also be changed by adding appropriate passive components to the usb signals.
copyright ? 201 2 future technology devi ces international limited 5 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 2 ft2232h block diagram figure 2 . 1 ft2232h block diagram for a description of each function please refer to section 4 . u s b p r o t o c o l e n g i n e a n d f i f o c o n t r o l u t m i p h y u s b d m u s b d p r r e f r e s e t g e n e r a t o r r e s e t # t e s t o s c i o s c o 1 . 8 v o l t l d o r e g u l a t o r v c c 3 v 3 i n v 1 . 8 o u t e e p r o m i n t e r f a c e e e c s e e s k e e d a t a p w r e n # s u s p e n d # 1 2 0 m h z d u a l p o r t t x b u f f e r 4 k b y t e s d u a l p o r t r x b u f f e r 4 k b y t e s b a u d r a t e g e n e r a t o r m p s s e / m u l t i - p u r p o s e u a r t / f i f o c o n t r o l l e r a d b u s 0 a d b u s 1 a d b u s 2 a d b u s 3 a d b u s 4 a d b u s 5 a d b u s 6 a d b u s 7 1 2 0 m h z a c b u s 0 a c b u s 7 a c b u s 5 a c b u s 1 a c b u s 2 a c b u s 3 a c b u s 4 a c b u s 6 1 2 0 m h z d u a l p o r t t x b u f f e r 4 k b y t e s d u a l p o r t r x b u f f e r 4 k b y t e s b a u d r a t e g e n e r a t o r m p s s e / m u l t i - p u r p o s e u a r t / f i f o c o n t r o l l e r b d b u s 0 b d b u s 1 b d b u s 2 b d b u s 3 b d b u s 4 b d b u s 5 b d b u s 6 b d b u s 7 1 2 0 m h z b c b u s 0 p w r s a v # / b c b u s 7 b c b u s 5 b c b u s 1 b c b u s 2 b c b u s 3 b c b u s 4 b c b u s 6
copyright ? 201 2 future technology devi ces international limited 6 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 table of contents 1 typi cal applications ................................ ................................ ...... 3 1.1 driver support ................................ ................................ .................... 3 1.2 part numbers ................................ ................................ ...................... 4 1.3 u sb compliant ................................ ................................ .................... 4 2 ft2232h block diagram ................................ ............................... 5 3 device pin out and signal description ................................ .......... 8 3.1 64 - pin lqfp and 64 - pin qfn package schematic symbol ................... 8 3.2 ft2232h pin descriptions ................................ ................................ ... 9 3.3 common pins ................................ ................................ .................... 10 3.4 configured pins ................................ ................................ ................ 12 3.4.1 ft2232h pins used in an rs232 interface ................................ ................................ ..... 12 3.4.2 ft2232h pins used in an ft245 style synchronous fifo interface ................................ ... 13 3.4.3 ft2232h pins used in an ft245 style asynchronous fifo interface ................................ . 14 3.4.4 ft2232h pins used in a synchronous or asynchronous bit - bang interface ........................ 15 3.4.5 ft2232h pins used in an mpsse ................................ ................................ .................. 16 3.4.6 ft2232h pins used as a fast serial interface ................................ ................................ 17 3.4.7 ft2232h pins configured as a cpu - style fifo interface ................................ ................. 18 3.4.8 ft2232h pins configured as a host bus emulation interface ................................ ........... 19 4 function description ................................ ................................ ... 20 4.1 key features ................................ ................................ ..................... 20 4.2 functional block descriptions ................................ ........................... 20 4.3 dual port ft232 uart interface mode description ........................... 22 4.3.1 dual port rs232 configuration ................................ ................................ .................... 22 4.3.2 dual port rs422 configuration ................................ ................................ .................... 23 4.3.3 dual port rs485 configuratio n ................................ ................................ .................... 25 4.4 ft245 synchronous fifo interface mode description ...................... 27 4.4.1 ft245 synchronous fifo read operation ................................ ................................ ..... 28 4.4.2 ft245 synchronous fifo write operation ................................ ................................ ..... 28 4.5 ft245 asynchronous fifo interface mode description ..................... 29 4.6 mpsse interface mode description. ................................ .................. 31 4.6.1 mpsse adaptive clocking ................................ ................................ ............................ 32 4.7 mcu host bus emulation mode ................................ ......................... 33 4.7.1 mcu host bus emulation mode signal timing C write cycle ................................ ............. 34 4.7.2 mcu host bus emulation mode signal timing C read cycl e ................................ ............. 35 4.8 fast opto - isolated serial interface mode description ...................... 37
copyright ? 201 2 future technology devi ces international limited 7 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.8.1 outgoing fast serial data ................................ ................................ ........................... 38 4.8.2 incoming fast serial data ................................ ................................ ........................... 38 4.8.3 fast opto - isolated serial data interface example ................................ .......................... 39 4.9 cpu - style fifo interface mode description ................................ ...... 40 4.10 synchronous and asynchronous bit - bang interface mode description ................................ ................................ ................................ 42 4.11 rs232 uart mode led interface description ................................ 44 4.12 send immediate / wake up (siwu#) ................................ ............ 45 ft2232h mode selection ................................ ................................ ........... 46 4.12.1 do i need an eeprom? ................................ ................................ ........................... 46 5 devices characteristics and ratings ................................ ........... 47 5.1 abso lute maximum ratings ................................ ............................... 47 5.2 dc characteristics ................................ ................................ ............. 48 5.3 esd tolerance ................................ ................................ ................... 50 6 ft2232h configurations ................................ ............................. 51 6.1 usb bus powered configuration ................................ ....................... 51 6.2 usb self powered configuration ................................ ....................... 53 6.3 oscillator configuration ................................ ................................ .... 55 7 eeprom configuration ................................ ................................ 56 8 package parameters ................................ ................................ ... 57 8.1 ft2232hq, qfn - 64 package dimensions ................................ .......... 57 8.2 ft2232hl, lqfp - 64 package dimensions ................................ ......... 58 8.3 solder reflow profile ................................ ................................ ........ 60 9 contact information ................................ ................................ ... 62 appendix a C list of figures and tables ................................ .................... 64 list of tables ................................ ................................ ............................. 64 appendix b C revision history ................................ ................................ ... 66
copyright ? 201 2 future technology devi ces international limited 8 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3 device pin out and signal description the 64 - pin lqfp and 64 - pin qfn have the same pin numbering for specific functions. this pin num bering is illustrated in the schematic symbol shown in figure 3 . 1 . 3.1 64 - pin lqfp and 64 - pin qfn package schematic symbol figure 3 . 1 ft2232h schematic symbol g n d 1 o s c i 2 o s c o 3 v p h y 4 g n d 5 r e f 6 d m 7 d p 8 v p l l 9 a g n d 1 0 g n d 1 1 v c o r e 1 2 t e s t 1 3 r e s e t # 1 4 g n d 1 5 a d b u s 0 1 6 a d b u s 1 1 7 a d b u s 2 1 8 a d b u s 3 1 9 v c c i o 2 0 a d b u s 4 2 1 a d b u s 5 2 2 a d b u s 6 2 3 a d b u s 7 2 4 g n d 2 5 a c b u s 0 2 6 a c b u s 1 2 7 a c b u s 2 2 8 a c b u s 3 2 9 a c b u s 4 3 0 v c c i o 3 1 a c b u s 5 3 2 a c b u s 6 3 3 a c b u s 7 3 4 g n d 3 5 s u s p e n d # 3 6 v c o r e 3 7 b d b u s 0 3 8 b d b u s 1 3 9 b d b u s 2 4 0 b d b u s 3 4 1 v c c i o 4 2 b d b u s 4 4 3 b d b u s 5 4 4 b d b u s 6 4 5 b d b u s 7 4 6 g n d 4 7 b c b u s 0 4 8 v r e g o u t 4 9 v r e g i n 5 0 g n d 5 1 b c b u s 1 5 2 b c b u s 2 5 3 b c b u s 3 5 4 v c c i o 5 6 b c b u s 4 5 5 b c b u s 5 5 7 b c b u s 6 5 8 b c b u s 7 5 9 p w r e n # 6 0 e e c l k 6 2 e e d a t a 6 1 e e c s 6 3 v c o r e 6 4 f t 2 2 3 2 h l
copyright ? 201 2 future technology devi ces international limited 9 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.2 ft2232h pin descriptions this section describes the operation of the ft2232h pins. both the lqfp and the qfn packages have the same function on each pin. the function of many pins is determined by the configuration of the ft22 32h. the following table details the function of each pin dependent on the configuration of the interface. each of the functions are described in the following table ( note: the convention used throughout this document for active low signals is the signal n ame followed by a #). pins marked ** default to tri - stated inp uts with an internal 75k? (approx) pull up resistor to vccio. ft2232h pin pin functions (depends on configuration) pin # pin name async serial (rs232) 245 fifo sync 245 fifo async bit - bang sync bit - bang mpsse fast serial interface cpu style fifo host bu s emulation channel a 16 adbus0 txd d0 d0 d0 d0 tck/sk uses channel b d0 ad0 17 adbus1 rxd d1 d1 d1 d1 tdi/do d1 ad1 18 adbus2 rts# d2 d2 d2 d2 tdo/di d2 ad2 19 adbus3 cts# d3 d3 d3 d3 tms/cs d3 ad3 21 adbus4 dtr# d4 d4 d4 d4 gpiol0 d4 ad4 22 adbus5 dsr# d5 d5 d5 d5 gpiol1 d5 ad5 23 adbus6 dcd# d6 d6 d6 d6 gpiol2 d6 ad6 24 adbus7 ri# d7 d7 d7 d7 gpiol3 d7 ad7 26 acbus0 txden rxf# rxf# ** ** gpioh0 cs# a8 27 acbus1 ** txe# txe# wrstb# wrstb# gpioh1 a0 a9 28 acbus2 ** rd# rd# rdstb# rdstb# gpioh2 rd# a10 29 acbus3 r xled# wr # wr # ** ** gpioh3 wr # a11 30 acbus4 t xled# siwua siwua siwua siwua gpioh4 siwua a12 32 acbus5 ** clkout ** ** ** gpioh5 ** a13 33 acbus6 ** oe# ** ** ** gpioh6 ** a1 4 34 acbus7 ** ** ** ** ** gpioh7 ** a15 channel b 38 bdbus0 txd d0 d0 d0 tck/sk fsdi d0 cs# 39 bdbus1 rxd d1 d1 d1 tdi/do fsclk d1 ale 40 bdbus2 rts# d2 d2 d2 tdo/di fsdo d2 rd# 41 bdbus3 cts# d3 d3 d3 tms/cs fscts d3 wr # 43 bdbus4 dtr# d4 d4 d4 gpiol0 d4 iordy 44 bdbus5 dsr# d5 d5 d5 gpiol1 d5 clkout 45 bdbus6 dcd# d6 d6 d6 gpiol2 d6 i/o0 46 bdbus7 ri# d7 d7 d7 gpiol3 d7 i/o1 48 bcbus0 txden rxf# ** ** gpioh0 cs# ** 52 bcbus1 ** txe# wrstb# wrstb# gpioh1 a0 ** 53 bcbus2 ** rd# rdstb# rdstb# gpioh2 rd# ** 54 bcbus3 r xled# wr # ** ** gpioh3 wr # ** 55 bcbus4 t xled# siwub siwub siwub gpioh4 siwub siwub ** 57 bcbus5 ** ** ** ** gpioh5 ** ** 58 bcbus6 ** ** ** ** gpioh6 ** ** 59 bcbus7 pwrsav # pwrsav # pwrsav # pwrsav # pwrsav # gpioh7 pwrsav # pwrsav# pwrsav# 60 pwren# pwren# pwren# pwren# pwren# pwren# pwren# pwren# pwren# pwren#
copyright ? 201 2 future technology devi ces international limited 10 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.3 common pins the operation of the following ft2232h pins are the same regardless of the configured mode: - pin no. name type description 12,37,64 vcore po wer input +1.8v input. core supply voltage input. 20,31,42,56 vccio power input +3.3v input. i/o interface power supply input. failure to connect all vccio pins will result in failure of the device. 9 vpll power input +3.3v input. internal phy pll powe r supply input. it is recommended that this supply is filtered using an lc filter. 4 vphy power input +3.3v input. internal usb phy power supply input. note that this cannot be connected directly to the usb supply. a +3.3v regulator must be used. it is re commended that this supply is filtered using an lc filter. 50 vregin power input +3.3v input. integrated 1.8v voltage regulator input. 49 vregout power output +1.8v output. integrated voltage regulator output. connect to vcore with 3.3uf filter capacitor . 10 agnd power input 0v analog ground. 1,5,11,15, 25,35,47,51 gnd power input 0v ground input. table 3 . 1 power and ground 36 suspend# suspend# suspend # suspend # suspend # suspend # susp end # suspend # suspend# suspend # configuration memory interface 63 eecs 62 eeclk 61 eedata
copyright ? 201 2 future technology devi ces international limited 11 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 pin no. name type description 2 osci input oscillator input. 3 osco output osc illator output. 6 ref input current reference C connect via a 12k? resistor @ 1% to gnd. 7 dm input usb data signal minus. 8 dp input usb data signal plus. 13 test input ic test pin C for normal operation should be connected to gnd. 14 reset# input r eset input (active low). 60 pwren# output active low power - enable output. pwren# = 0: normal operation. pwren# =1 : usb suspend mode or device has not been configured. this can be used by external circuitry to power down logic when device is in usb suspe nd or has not been configured. 36 suspend# output active low when usb is in suspend mode. 59 pwrsav# input usb power save input. this is an eeprom configurable option used when the ft2232h is used in a self powered mode and is used to prevent forcing cur rent down the usb lines when the host or hub is powered off. pwrsav# = 1 : normal operation pwrsav# = 0 : ft2232h forced into suspend mode. pwrsav# can be connected to gnd (via a 10k? resistor) and another resistor (e.g. 4k7) connected to the vbus of the usb connector. when this input goes high, then it indicates to the ft2232h that it is connected to a host pc. when the host or hub is powered down then the ft2232h is held in suspend mode. table 3 . 2 common f unction pins pin no. name type description 63 eecs i/o eeprom C 62 eeclk output clock signal to eeprom. tri - state during device reset. when not in reset, this outputs the eeprom clock. 61 eedata i/o eeprom C table 3 . 3 eeprom interface group
copyright ? 201 2 future technology devi ces international limited 12 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4 configured pins the following sections describe the function of the configurable pins referred to in the table given in section 3.2 which is determined by how the ft 2232h is configured. 3.4.1 ft2232h pins used in an rs232 interface the ft2232h channel a or channel b can be configured as an rs232 interface. when configured in this mode, the pins used and the descriptions of the signals are shown in table 3 . 4 . channel a pin no. channel b pin no. name type rs232 configuration description 16 38 txd output txd = transmitter output 17 39 rxd input rxd = receiver input 18 40 rts# output rts# = ready to send handshake output 19 41 cts# input cts# = clear to send handshake input 21 43 dtr# output dtr# = data transmit ready modem signaling line 22 44 dsr# input dsr# = data set ready modem signaling line 23 45 dcd# input dcd# = data carrier detect modem signaling line 24 46 ri# input ri# = ring indicator control input. when the remote wake up option is enabled in the eeprom, taking ri# low can be used to resume the pc usb host controller from suspend . ( also see note 1, 2, 3 in section 4.12 ) 26 48 t xden output txden = (ttl level). for use with rs485 level converters. 29 54 rxled # output rxled = receive signaling output when data is transferred from ft2232h to usb host . pulses low when receiving data (rxd) via usb. this should be connected to an led . 30 55 txled # output txled = transmit signaling output when data is transferred from usb host to ft2232h . pulses low when transmitting data (txd) via usb. this should be connected to an led. table 3 . 4 chann el a and channel b rs232 configured pin descriptions
copyright ? 201 2 future technology devi ces international limited 13 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4.2 ft2232h pins used in an ft245 style synchronous fifo interface the ft2232h only channel a can be configured as a ft245 style synchronous fifo interface. when configured in this mode, the pins used and the descriptions of the signals are shown in table 3 . 5 . to enter this mode the external eeprom must be set to make port a 245 mode. a software command (set bit mode option) is then sent by the application to the ftdi driver to tell the chip to enter single channel synchronous fifo mode. in this mode the ?b? channel is not available as all resources have been switched onto channel a. in this mode, data is written or read on the rising edge of the clkout. ch annel a pin no. name type ft 245 configuration description 24,23,22,21, 19,18,17,16 adbus[7:0] i/o d7 to d0 bidirectional fifo data. this bus is normally input unless oe# is low. 26 rxf# output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by driving rd# low. when in synchronous mode, data is transferred on every clock that rxf# and rd# are both low. note that the oe# pin must be driven low at least 1 clock period before asserting rd# low. 27 tx e# output when high, do not write data into the fifo. when low, data can be written into the fifo by driving wr # low. when in synchronous mode, data is transferred on every clock that txe# and wr # are both low. 28 rd# input enables the current fifo data b yte to be driven onto d0...d7 when rd# goes low. the next fifo data byte (if available) is fetched from the receive fifo buffer each clkout cycle until rd# goes high. 29 wr # input enables the data byte on the d0...d7 pins to be written into the transmit f ifo buffer when wr # is low. the next fifo data byte is written to the transmit fifo buffer each clkout cycle until wr # goes high. 32 clkout output 60 mhz clock driven from the chip. all signals should be synchronized to this clock. 33 oe# input output en able when low to drive data onto d0 - 7. this should be driven low at least 1 clock period before driving rd# low to allow for data buffer turn - around. 30 siwu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in sus pend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cause the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is str obed low any data in the device tx buffer will be sent out over usb on the next bulk - in request from the drivers regardless of the pending packet size. this can be used to optimize usb transfer speed for some applications. tie this pin to vccio if not used . (also see note 1, 2, 3 in section 4.12 ) table 3 . 5 channel a ft245 style synchronous fifo configured pin descriptions for a functional description of this mode, please refer to section 4.4
copyright ? 201 2 future technology devi ces international limited 14 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4.3 ft2232h pins used in an ft245 style asynchronous fifo interface the ft2232h channel a or channel b can be configured as a ft245 asynchronous fifo interface. when configured in this mode, the pins used and the desc riptions of the signals are shown in table 3 . 6 . to enter this mode the external eeprom must be set to make port a or b or both 245 mode. in this mode, data is written or read on th e falling edge of the rd# or wr # signals. channel a pin no. channel b pin no. name type ft 245 configuration description 24,23,22,21, 19,18,17,16 46,45,44,43, 41,40,39,38 channel a = adbus[7:0] channel b = bdbus[7:0] i/o d7 to d0 bidirectional fifo data. this bus is normally input unless rd# is low. 26 48 rxf# output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by driving rd# low. when rd# goes high again rxf# will always go high and only become low again if there is an other byte to read. during reset this signal pin is tri - state, but pulled up to vccio via an internal 200k resistor. 27 52 txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing wr # high, then low. during reset this signal pin is tri - state, but pulled up to vccio via an internal 200k resistor. 28 53 rd# input enables the current fifo data byte to be driven onto d0...d7 when rd# goes low. fetches the next fifo data byte (if available) from the rece ive fifo buffer when rd# goes high. 29 54 wr # input writes the data byte on the d0...d7 pins into the transmit fifo buffer when wr # goes from high to low. 30 55 siwu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in suspend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cause the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is strobed low any data in the device tx buffer will be sent out over usb on the next bulk - in request from the drivers regardless of the pending packet size. this can be used to optimize usb transfer speed for some applications. tie this pin to vccio i f not used. (also see note 1, 2, 3 in section 4.12 ) table 3 . 6 channel a and channel b ft245 style asynchronous fifo configured pin descriptions
copyright ? 201 2 future technology devi ces international limited 15 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4.4 ft2232h pins used in a synchrono us or asynchronous bit - bang interface the ft2232h channel a or channel b can be configured as a synchronous or asynchronous bit - bang interface. bit - bang mode is a special ftdi ft2232h device mode that changes the 8 io lines on either (or both) channels int o an 8 bit bi - directional data bus. there are two types of bit - bang modes: synchronous and asynchronous. when configured in any bit - bang mode, the pins used and the descriptions of the signals are shown in table 3 . 7 channel a pin no. channel b pin no. name type configuration description 24,23,22,21 , 19,18,17,16 46,45,44,43, 41,40,39,38 channel a = adbus[7:0] channel b = bdbus[7:0] i/o d7 to d0 bidirectional bit - bang parallel i/o data pins 27 52 wrstb# o utput write strobe, active low output indicates when new data has been written to the i/o pins from the host pc (via the usb interface). 28 53 rdstb# output read strobe, this output rising edge indicates when data has been read from the parallel i/o pins and sent to the host pc (via the usb interface) . 30 55 siwu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in suspend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cau se the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is strobed low any data in the device tx buffer will be sent out over usb on the next bulk - in request fr om the drivers regardless of the pending packet size. this can be used to optimize usb transfer speed for some applications. tie this pin to vccio if not used. (also see note 1, 2, 3 in section 4.12 ) table 3 . 7 channel a and channel b synchronous or asynchronous bit - bang configured pin descriptions for a functional description of this mode, please refer to section 4.10 synchronous and asynchronous bit - bang interface mode description .
copyright ? 201 2 future technology devi ces international limited 16 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4.5 ft2232h pins used in an mpsse the ft2232h channel a and channel b each have a multi - protocol sync hronous serial engine (mpsse). each mpsse can be independently configured to a number of industry standard serial interface protocols such as jtag, i2c or spi, or it can be used to implement a proprietary bus protocol. for example, it is possible to use o ne of the ft2232h?s channels to connect to an sram configurable fpga such as supplied by altera or xilinx. the fpga device would normally be un - configured (i.e. have no defined function) at power - up. application software on the pc could use the mpsse to do wnload configuration data to the fpga over usb. this data would define the hardware function on power up. the other ft2232h channel would be available for another function. alternatively each mpsse can be used to control a number of gpio pins. when configu red in this mode, the pins used and the descriptions of the signals are shown table 3 . 6 channel a pin no. channel b pin no. name type mpsse configuration description 16 38 tck/sk output clock signal outpu t. for example: jtag C tck, test interface clock spi C sk, serial clock 17 39 tdi/do output serial data output. for example: jtag C tdi, test data input spi C do 18 40 tdo/di input serial data input. for example: jtag C tdo, test data output spi C di, se rial data input 19 41 tms/cs output output signal select. for example: jtag C tms, test mode select spi C cs, serial chip select 21 43 gpiol0 i/o general purpose input/output 22 44 gpiol1 i/o general purpose input/output 23 45 gpiol2 i/o general purp ose input/output 24 46 gpiol3 i/o general purpose input/output 26 48 gpioh0 i/o general purpose input/output 27 52 gpioh1 i/o general purpose input/output 28 53 gpioh2 i/o general purpose input/output 29 54 gpioh3 i/o general purpose input/output 30 55 gpioh4 i/o general purpose input/output 32 57 gpioh5 i/o general purpose input/output 33 58 gpioh6 i/o general purpose input/output 34 59 gpioh7 i/o general purpose input/output
copyright ? 201 2 future technology devi ces international limited 17 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 table 3 . 8 chan nel a and channel b mpsse configured pin descriptions for a functional description of this mode, please refer to section 4.6 mpsse interface mode description. 3.4.6 ft2232h pins used as a fast serial interface the ft2232h channel b can be configured for use with high - speed optical bi - directional isolated serial data transfer: fast serial interface. (not available on channel a). a proprietary ftdi protocol designed to allow galvanic isolated devices to communicate synchronously with the ft2232h using just 4 signal wires (over two dual opto - isolators), and two power lines. the peripheral circuitry controls the data transfer rate in both directio ns, whilst maintaining full data integrity. maximum usb full speed data rates can be achieved. both ?a? and ?b? channels can communicate over the same 4 wire interface if desired. when configured in this mode, the pins used and the descriptions of the sign als are shown in table 3 . 9 . channel b pin no. name type fast serial interface configuration description 38 fsdi input fast serial data input. 39 fsclk input fast serial clock input. clock input to ft22 32h chip to clock data in or out. 40 fsdo output fast serial data output. 41 fscts output fast serial clear to send signal output. driven low to indicate that the chip is ready to send data table 3 . 9 channe l b fast serial interface configured pin descriptions for a functional description of this mode, please refer to section 4.8 fast opto - isolated se rial interface mode description
copyright ? 201 2 future technology devi ces international limited 18 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4.7 ft2232h pins configured as a cpu - style fifo interface the ft2232h channel a or channel b can be configured in a cpu - style fifo interface mode which allows a cpu to interface to usb via the f t2232h. this mode is enabled in the external eeprom. when configured in this mode, the pins used and the descriptions of the signals are shown in table 3 . 10 channel a pin no. channel b pin no. name type fast serial interface configuration description 24,23,22,21 , 19,18,17,16 46,45,44,43 , 41,40,39,38 channel a = adbus[7:0] channel b = bdbus[7:0] i/o d7 to d0 bidirectional data bus 26 48 cs# input active low chip select input 27 52 a0 input address bit a 0 28 53 rd# input active low fifo read input 29 54 wr # input active low fifo write input table 3 . 10 channel a and channel b cpu - style fifo interface configured pin descriptions for a functional description of this mode, please refer to section 4.9 cpu - style fifo interface mode description
copyright ? 201 2 future technology devi ces international limited 19 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 3.4.8 ft2232h pins configured as a host bus e mulation interface the ft2232h can be used to combine channel a and channel b to be configured as a host bus emulation interface mode which emulates a standard 8048 or 8051 mcu host. when configured in this mode, the pins used and the descriptions of the signals are shown in tabl e 3 . 11 pin no. name type fast serial interface configuration description 24,23,22,21, 19,18,17,16 adbus[7:0] i/o multiplexed bidirectional address/data bus ad7 to ad0 34,33,32, 30, 29,28,27,26 a[15:8] output extended address a15 to a8 38 cs# output active low chip select device during read or write. 39 ale output positive pulse to latch the address 40 rd# output active low read output. 41 wr# output active low write out put. (data is setup before wr# goes low, and is held after wr# goes high) 43 iordy input extends the time taken to perform a read or write operation if driven low. pull up to vcore if not being used. 44 clkout output master clock. outputs the clock sig nal being used by the configured interface. 45 i/o0 i/o mpsse mode instructions to set / clear or read the high byte of data can be used with this pin. please refer to application note an_108 for operation of these instructions. 46 i/o1 i/o mpsse mode instructions to set / clear or read the high byte of data can be used with this pin. in addition this pin has instructions which will make the controller wait until it is high, or wait until it is low. this can be used to connect to an irq pin of a periphe ral chip. the ft2232h will wait for the interrupt, and then read the device, and pass the answer back to the host pc. i/o1 must be held in input mode if this option is used. please refer to application note an_108 for operation of these instructions. tabl e 3 . 11 channel a and channel b host bus emulation interface configured pin descriptions for a functional description of this mode, please refer to section 4.7 mcu host bus emulation mode
copyright ? 201 2 future technology devi ces international limited 20 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4 function description the ft2232h usb 2.0 high speed (480mb/s) to uart/fifo is one of ftdi?s 5 th generation of ics. it has the capability of being configured in a variety of industry standard serial or parallel interfaces. the ft2232h has two independent configurable interfaces. each interface can be configured as uart, fifo, jtag, spi, i2c or bit - bang mode with independent baud rate generators. in addition to thes e, the ft2232h supports a host bus emulation mode, a cpu - style fifo mode and a fast opto - isolated serial interface mode. 4.1 key features usb high speed to dual interface . the ft2232h is a usb 2.0 high speed (480mbits/s) to dual independent flexible and config urable parallel/serial interfaces. functional integration . the ft2232h integrates a usb protocol engine which controls the physical universal transceiver macrocell interface (utmi) and handles all aspects of the usb 2.0 high speed interface. the ft222h in cludes an integrated +1.8v low drop - out (ldo) regulator and 12mhz to 480mhz pll. it also includes 4kbytes tx and rx data buffers per interface. the ft2232h effectively integrates the entire usb protocol on a chip with no firmware required. mpsse .multi - pur pose synchronous serial engines (mpsse), capable of speeds up to 30 mbits/s, provides flexible synchronous interface configurations. data transfer rate. the ft2232h support s a data transfer rate up to 12 mbaud when configured as an rs232/rs422/rs485 uart interface or greater than 25 mbytes/second over a synchronous parallel fifo interface. please note the ft2232h do es not support the baud rates of 7 mbaud 9 mbaud, 10 mbaud and 11 mbaud . latency timer. this is really a feature of the driver and is used to as a timeout to flush short packets of data back to the pc. the default is 16ms, but it can be altered between 0ms and 25 5 ms . at 0ms latency you get a packet transfer on every high speed microframe. 4.2 functional block descriptions dual multi - purpose uart/fif o controllers. the ft2232h has two independent uart/fifo controllers. these control the uart data, 245 fifo data, opto isolation (fast serial) or control the bit - bang mode if selected by setup command. each multi - purpose uart/fifo controller also contain a n mpsse (multi protocol synchronous serial engine) which can be used independently of each other. using this mpsse, the multi - purpose uart/fifo controller can be configured, under software command, to have 1 mpsse + 1 uart / 245 fifo (each uart / 245 can be set to bit bang mode to gain extra i/o if required) or 2 mpsse. usb protocol engine and fifo control. the usb protocol engine controls and manages the interface between the utmi phy and the fifos of the chip. it also handles power management and the usb protocol specification. dual port fifo tx buffer (4kbytes per interface). data from the host pc is stored in these buffers to be used by the multi - purpose uart/fifo controllers. this is controlled by the usb protocol engine and fifo control block. dual po rt fifo rx buffer (4kbytes per interface). data from the multi - purpose uart/fifo controllers is stored in these blocks to be sent back to the the host pc when requested. this is controlled by the usb protocol engine and fifo control block. reset generator C the integrated reset generator cell provides a reliable power - on reset to the device internal circuitry at power up. the reset# input pin allows an external device to reset the ft2232h. reset# should be tied to vccio (+3.3v) if not being used. independen t baud rate generators C the baud rate generators provides a x16 or a x10 clock input to the uart?s from a 120mhz reference clock and consists of a 14 bit pre - scaler and 4 register bits which
copyright ? 201 2 future technology devi ces international limited 21 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 provide fine tuning of the baud rate (used to divide by a number plus a fraction). this determines the baud rate of the uart which is programmable from 183 baud to 12 million baud. the ft2232h does not support the baud rates of 7 mbaud 9 mbaud, 10 mbaud and 11 mbaud . see ftdi application note an232b - 05 on the ftdi website ( www.ftdichip.com ) for more details. +1.8v ldo regulator. the +1.8v ldo regulator generates the +1. 8 volts for the core and the usb transceiver cell. its input (vregin) must be connected to a +3.3v external power source. it is also recommended to add an external filtering capacitor to the vregin. there is no direct connection from the +1.8v output (vreg out) and the internal functions of the ft2232h. the pcb must be routed to connect vregout to the pins that require the +1.8v including vregin. utmi phy . the universal transceiver macrocell interface (utmi) physical interface cell. this block handles the fu ll speed / high speed serdes (serialise C deserialise) function for the usb tx/rx data. it also provides the clocks for the rest of the chip. a 12 mhz crystal should be connected to the osci and osco pins. a 12k ohm resistor should be connected between ref and gnd on the pcb. the utmi phy functions include: ? supports 480 mbit/s high speed (hs)/ 12 mbit/s full speed (fs), fs only and low speed (ls) ? sync/eop generation and checking ? data and clock recovery from serial stream on the usb. ? bit - stuffing/unst uffing; bit stuff error detection. ? manages usb resume, wake up and suspend functions. ? single parallel data clock output with on - chip pll to generate higher speed serial data clocks. eeprom interface . when used without an external eeprom the ft2232h defaul ts to a usb to dual asynchronous serial port device. adding an external 93c46 (93c56 or 93c66) eeprom allows each of the chip?s channels to be independently configured as a serial uart (rs232 mode), parallel fifo (245) mode or fast serial (opto isolation). the external eeprom can also be used to customise the usb vid, pid, serial number, product description strings and power descriptor value of the ft2232h for oem applications. other parameters controlled by the eeprom include remote wake up, soft pull down on power - off and i/o pin drive strength. the eeprom should be a 16 bit wide configuration such as a microchip 93lc46b or equivalent capable of a 1mbit/s clock rate at vcc = +3.00v to 3.6v. the eeprom is programmable in - circuit over usb using a utility pro gram called mprog available from ftdi?s web site ( www.ftdichip.com ). this allows a blank part to be soldered onto the pcb and programmed as part of the manufacturing and test process. if no eeprom is connected (or the eeprom is blank), the ft2232h will de fault to dual serial ports. the device uses its built - in default vid (0403) , pid (6010) product description and power descriptor value. in this case, the device will not have a serial number as part of the usb descriptor.
copyright ? 201 2 future technology devi ces international limited 22 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.3 dual port ft232 uart interface mode description the ft2232h can be configured in similar uart modes as the ftdi ft232 devices. the following examples illustrate how to configure the ft2232h with an rs232, rs422 or rs485 interface. the ft2232 can be configured as a mixture of these inte rfaces. 4.3.1 dual port rs232 configuration figure 4 . 1 illustrates how the ft2232h can be configured with an rs232 uart interface. this can be repeated for channel b to provide a dual rs232, but has been omitte d for clarity. figure 4 . 1 rs232 configuration g n d 1 o s c i 2 o s c o 3 v p h y 4 g n d 5 r e f 6 d m 7 d p 8 v p l l 9 a g n d 1 0 g n d 1 1 v c o r e 1 2 t e s t 1 3 r e s e t # 1 4 g n d 1 5 1 6 1 7 1 8 1 9 v c c i o 2 0 2 1 2 2 2 3 2 4 g n d 2 5 2 6 2 7 2 8 2 9 3 0 v c c i o 3 1 3 2 3 3 3 4 g n d 3 5 s u s p e n d # 3 6 v c o r e 3 7 3 8 3 9 4 0 4 1 v c c i o 4 2 4 3 4 4 4 5 4 6 g n d 4 7 4 8 v r e g o u t 4 9 v r e g i n 5 0 g n d 5 1 5 2 5 3 5 4 v c c i o 5 6 5 5 5 7 5 8 5 9 p w r e n # 6 0 e e c l k 6 2 e e d a t a 6 1 e e c s 6 3 v c o r e 6 4 v i n v o u t g n d l d o + 3 . 3 v g n d v b u s 1 d - 2 d + 3 g n d 4 g n d 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f g n d g n d g n d g n d g n d 4 . 7 u f 4 . 7 u f g n d g n d + 1 . 8 v + 3 . 3 v + 1 . 8 v + 3 . 3 v 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f + 1 . 8 v + 1 . 8 v + 1 . 8 v + 3 . 3 v + 3 . 3 v + 3 . 3 v + 3 . 3 v g n d g n d g n d g n d g n d g n d g n d + 3 . 3 v + 3 . 3 v 1 2 k 1 k g n d + 3 . 3 v c s 1 s c l 2 d 3 q 4 g n d 5 o r g 6 d u 7 v c c 8 9 3 c 4 6 g n d g n d g n d + 3 . 3 v + 3 . 3 v 2 . 2 k 1 0 k 1 0 k 1 0 k 1 3 1 2 m h z e e c l k e e d a t a g n d 1 2 3 4 5 6 7 8 9 1 1 1 0 c o n 1 r s 2 3 2 - a d c d 1 r x d 1 t x d 1 d t r 1 g n d d s r 1 r t s 1 c t s 1 r i 1 1 0 0 n f g n d e e c s p w r e n t t l _ t x d 1 t t l _ r t s 1 t t l _ r x d 1 t t l _ c t s 1 t t l _ d t r 1 t t l _ d c d 1 t t l _ d s r 1 t t l _ r i 1 1 3 v - 3 9 c 1 - 2 4 1 4 1 2 c 1 + 2 8 1 0 s h d n 2 2 1 1 2 3 v + 2 7 v c c 2 6 g n d 2 5 5 1 5 1 9 8 4 6 7 1 8 1 7 1 6 c 2 + 1 c 2 - 2 2 1 2 0 m a x 3 2 4 1 e u i t t l _ t x d 1 t t l _ r t s 1 t t l _ d t r 1 t t l _ r x d 1 t t l _ c t s 1 t t l _ d c d 1 t t l _ d s r 1 t t l _ r i 1 d c d 1 r x d 1 t x d 1 d t r 1 d s r 1 r t s 1 c t s 1 r i 1 g n d 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f g n d g n d + 3 . 3 v p w r e n # s u s p e n d s u s p e n d r x d _ l e d t x d _ l e d 2 2 0 2 2 0 l e d 1 l e d 2 + 3 . 3 v + 3 . 3 v t x d _ l e d r x d _ l e d a d b u s 0 a d b u s 1 a d b u s 2 a d b u s 3 a d b u s 4 a d b u s 5 a d b u s 6 a d b u s 7 b d b u s 0 b d b u s 1 b d b u s 2 b d b u s 3 b d b u s 4 b d b u s 5 b d b u s 6 b d b u s 7 b c b u s 0 b c b u s 1 b c b u s 2 b c b u s 3 b c b u s 4 b c b u s 5 b c b u s 6 b c b u s 7 a c b u s 0 a c b u s 1 a c b u s 2 a c b u s 3 a c b u s 4 a c b u s 5 a c b u s 6 a c b u s 7 0 ? 2 7 p f 2 7 p f 3 . 3 u f
copyright ? 201 2 future technology devi ces international limited 23 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.3.2 dual port rs422 configuration figure 4 . 2 illustrates how the ft2232h can be conf igured as a dual rs422 interface. figure 4 . 2 dual rs422 configuration in this case both channel a and channel b are configured as uart operating at ttl levels and a level converter device (full duplex rs485 transceiver) is used to convert the ttl level signals from the
copyright ? 201 2 future technology devi ces international limited 24 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 ft 2 232h to rs422 levels. the pwren# signal is used to power down the level shifters such that they operate in a low quiescent current when the usb interface is in suspend mode.
copyright ? 201 2 future technology devi ces international limited 25 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.3.3 dual port rs4 85 configuration figure 4 . 3 illustrates how the ft2232h can be configured as a dual rs485 interface. figure 4 . 3 dual rs485 configuration in this case both channel a and channel b are configured as rs485 operating at ttl levels and a level converter device (half duplex rs485 transceiver) is used to convert the ttl level signals f rom the ft232h to rs485 levels. it has separate enables on both the transmitter and receiver. with rs485, the transmitter is only enabled when a character is being transmitted from the uart. the txden pins on the ft2232h are provided for exactly that purpose, and so the transmitter enables are wired to the txden?s. the receiver enable is active low, so it is wired to the pwren# pin to disable the receiver when in usb suspend mode.
copyright ? 201 2 future technology devi ces international limited 26 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 rs485 is a multi - drop network C i.e. many devices can communicate with each other over a single two wire cable connection. the rs485 cable requires to be te rminated at each end of the cable. links are provided to allow the cable to be terminated if the device is physically positioned at either end of the cable. in this example the data transmitted by the ft2232h is also received by the device that is transmi tting. this is a common feature of rs485 and requires the application software to remove the transmitted data from the received data stream. with the ft2232h it is possible to do this entirely in hardware C simply modify the schematic so that rxd of the ft 2 232h is the logical or of the level converter device receiver output with txden using an hc32 or similar logic gate with the ft2 232h it is possible to do this entirely in hardware C simply modify the schematic so that rxd of the ft2 232h is the logical or of the level converter device receiver output with txden using an hc32 or similar logic gate
copyright ? 201 2 future technology devi ces international limited 27 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.4 ft245 synchronous fifo interface mode description when channel a is configured in an ft245 synchronous fifo interface mode the io timing of the signals used are shown in figure 4 . 4 , which shows details for read and write accesses. the timings are shown in table 4.1 note that only a read or a write cycle can be performed at any one time. data is read or written on the rising edge of the clkout clock. figure 4 . 4 ft245 synchronous fifo interface signal waveforms
copyright ? 201 2 future technology devi ces international limited 28 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 name minimum typical maximum units desc ription t1 16.67 16.67 ns clkout period t2 7.5 8.33 9.17 ns clkout high period t3 7.5 8.33 9.17 ns clkout low period t4 1 7.15 ns clkout to rxf# t5 1 7.15 ns clkout to read data valid t6 1 7.15 ns oe# to read data valid t7 8 16.67 ns oe # setup time t8 0 ns oe# hold time t9 8 16.67 ns rd# setup time to clkout (rd# low afteroe# low) t10 0 ns rd# hold time t11 1 7.15 ns clkout to txe# t12 8 16.67 ns write data setup time t13 0 ns write data hold time t14 8 16.67 ns wr# setup time to clkout (wr# low after txe# low) t15 0 ns wr# hold time table 4 . 1 ft245 synchronous fifo interface signal timings this single channel mode uses a synchronous interface to get high da ta transfer speeds. the chip drives a 60 mhz clkout clock for the external system to use. note that asynchronous fifo mode must be selected on both channels before selecting the synchronous fifo mode in software. 4.4.1 ft245 synchronous fifo read operation a rea d operation is started when the chip drives rxf# low. the external system can then drive oe# low to turn around the data bus drivers before acknowledging the data with the rd# signal going low. the first data byte is on the bus after oe# is low. the extern al system can burst the data out of the chip by keeping rd# low or it can insert wait states in the rd# signal. if there is more data to be read it will change on the clock following rd# sampled low. once all the data has been consumed, the chip will drive rxf# high. any data that appears on the data bus, after rxf# is high, is invalid and should be ignored. 4.4.2 ft245 synchronous fifo write operation a write operation can be started when txe# is low . wr # is brought low when the data is valid. a burst operation can be done on every clock providing txe# is still low. the external system m ust monitor txe# and its own wr # to check that data has been accepted. both txe# and wr # must be low for data to be accepted.
copyright ? 201 2 future technology devi ces international limited 29 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.5 ft245 asynchronous fifo interface mode description the ft2232h can be configured as a dual channel asynchronous fifo interface. this mode is similar to the synchronous fifo interface with the exception that the data is written to or read from the fif o on the falling edge of the wr # or rd# signals. this m ode does not provide a clkout signal and it does not expect an oe# input signal. the following diagrams illustrate the asynchronous fifo mode timing. figure 4 . 5 ft245 asynchronous fifo interface read signal waveforms figure 4 . 6 ft245 asynchronous fifo interface write signal waveforms
copyright ? 201 2 future technology devi ces international limited 30 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 name minimum typical maximum units description t1 1 14 ns rd# inactive to rx# t2 49 ns rxf# inactive after rd# cycle t3 1 14 ns rd# to data t4 30 ns rd# active pulse width t5 0 ns rd# active after rxf# t6 1 14 ns wr# active to txe# inactive t7 49 ns txe# inactive after wr# cycle t8 5 ns data to wr# active setup time t9 5 ns data hold time after wr# ina ctive t10 30 ns wr# active pulse width t11 0 ns wr# active after txe# table 4 . 2 asynchronous fifo timings (based on standard drive level outputs)
copyright ? 201 2 future technology devi ces international limited 31 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.6 mpsse interface mode description. mpsse mode is design ed to allow the ft2232h to interface efficiently with synchronous serial protocols such as jtag, i2c and spi bus. it can also be used to program sram based fpga?s over usb. the mpsse interface is designed to be flexible so that it can be configured to allo w any synchronous serial protocol (industry standard or proprietary) to be implemented using the ft2232h. mpsse is available on channel a and channel b. mpsse is fully configurable, and is programmed by sending commands down the data stream. these can be s ent individually or more efficiently in packets. mpsse is capable of a maximum sustained data rate of 30 mbits/s . when a channel is configured in mpsse mode, the io timing and signals used are shown in figure 4 . 7 and table 4 . 3 these show timings for clkout=30mhz. clkout can be divided internally to be provide a slower clock. figure 4 . 7 mpsse signal wavefor ms table 4 . 3 mpsse signal timings mpsse mode is enabled using set bit bang mode driver command. a hex value of 2 will enable it, and a hex value of 0 will reset the device. see appli cation note an2232l - 02, bit mode functions for the ft2232d for more details and examples. the mpsse command set is fully described in application note an_108 C command processor for mpsse and mcu host bus emulation modes . the following additional appli cation notes are available for configuring the mpsse : ? an_109 C programming guide for high speed ftci2c dll ? an_110 C programming guide for high speed ftcjtag dll ? an_111 C programming guide for high speed ftcspi dll name minimum typical maximum units description t1 33.33 ns clkout period t2 15 16.67 ns clkout high period t3 15 16.67 ns clkout low period t4 1 7.15 ns clkout to tdi/do delay t5 0 ns tdo/di hold time t6 11 tdo/di setup time
copyright ? 201 2 future technology devi ces international limited 32 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.6.1 mpsse adaptive clocking adaptive c locking is a new mpsse feature added to the ft2232h mpsse engine. the mode is effectively handshaking the clk signal with a return clock rtck. this is a technique used by arm processors. the ft2232h will assert the clk line and wait for the rtck to be retu rned from the target device to gpio l3 line before changing the tdo (data out line). figure 4 . 8 adaptive clocking interconnect figure 4 . 9 : adaptive clocking waveform. adaptive clocking is not enabled by default. see: an_108 command processor for mpsse and mcu host bus emulation modes. f t 2 2 3 2 h a r m c p u r t c k t c k t d o g p i o l 3 t d o t c k r t c k t d o c h a n g e s o n f a l l i n g e d g e o f t c k
copyright ? 201 2 future technology devi ces international limited 33 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.7 mcu host bus emulation mode mcu host bus emulation mode uses bo th of the ft2232h?s a and b channel interfaces to make the chip emulate a standard 8048/8051 mcu host bus. this allows peripheral devices for these mcu families to be directly connected to usb via the ft2232h. the lower 8 bits (ad7 to ad0) is a multiplex ed address / data bus. a15 to a 8 provide upper (extended) addresses. there are 4 basic operations: - 1) read (does not change a15 to a8) 2) read extended (changes a15 to a8) 3) write (does not change a15 to a8) 4) write extended (changes a15 to a8) mcu host b us emulation mode is enabled using set bit bang mode driver command. a hex value of 8 will enable it, and a hex value of 0 will reset the device. the ft2232h operates in the same way as the ft2232d. see application note an2232 - 02, bit mode functions for t he ft2232d for more details and examples. the mcu host bus emulation mode command set is fully described in application note an_108 C command processor for mpsse and mcu host bus emulation modes . when mcu host bus emulation mode is enabled the io signal lines on both channels work together and the pins are configured as described in tabl e 3 . 11 . the following sections give some details of the read and write cycle waveforms and timings. the clkout output clock can operate up to 60mhz. in host bus emulation mode the clock divisor has no effect. the clock divisor is used for serial data and is a different part of the mpsse block. in host bus emulation the 60mhz clock is always output and doesn?t change with any commands.
copyright ? 201 2 future technology devi ces international limited 34 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.7.1 mcu host bus emulation mode signal timing C write cycle figure 4 . 10 mcu host bus emulation mode signal waveforms C write cycle table 4 . 4 mcu host bus emulation mode signal timings C write cycle when div by 5 is on the device will return 2 bytes when doing a read. when it is off the device will return 1 byte when doing a read. the clock period is 16.67 ns so most d evices would need the div by 5 to be set on. iordy can be held low permanently to extend all cycles.
copyright ? 201 2 future technology devi ces international limited 35 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.7.2 mcu host bus emulation mode signal timing C read cycle figure 4 . 11 mcu host bus emulation mode signal waveforms C read cycle table 4 . 5 mcu host bus emulation mode signal timings C read cycle when div by 5 is on the device will return 2 bytes when doing a read. when it is off the device will return 1 byte when doing a read. the clock period is 16.67 ns so most devices would need the div by 5 to be set on. iordy can be held low permanently to extend all cycles.
copyright ? 201 2 future technology devi ces international limited 36 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 an example of the mcu host emulation interface enabling a usb inter face to can bus using a canbus controller is shown in figure 4 . 12 figure 4 . 12 mcu host emulation example using a canbus controller i / o 0 i / o 1 iordy # ft 2232 h sja 1000 canbus controller address / data bus ad [ 7 : 0 ] wr # rd # ad [ 7 : 0 ] cs # wr # ale rd # cs # ale / as vcc mode vcc int # rx tx canbus transeiver can bus
copyright ? 201 2 future technology devi ces international limited 37 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.8 fast opto - isolated se rial interface mode description fast opto - isolated serial interface mode provides a method of communicating with an external device over usb using 4 wires that can have opto - isolators in their path, thus providing galvanic isolation between systems. if eit her channel a or channel b is enabled in fast opto - isolated serial mode then the pins on channel b are switched to the fast serial interface configuration. the i/o interface for fast serial mode is always on channel b, even if both channels are being used in this mode. an address bit is used to determine the source or destination channel of the data. it therefore makes sense to always use at least channel b or both for fast serial mode, but not a own its own. fast serial mode is enabled by setting the appro priate bits in the external eeprom. the fast serial mode can be held in reset by setting a bit value of 10 using the set bit bang mode command. while this bit is set the device is held reset C data can be sent to the device, but it will not be sent out by the device until the device is enabled again. this is done by sending a bit value of 0 using the set bit mode command. see application note an2232l - 02, bit mode functions for the ft2232d for more details and examples. when either channel b or both channe l a and b are configured in fast opto - isolated serial interface mode the io timing of the signals used are shown in figure 4 . 13 and the timings are shown in table 4 . 6 figure 4 . 13 fast opto - isolated serial interface signal waveforms table 4 . 6 fast opto - isolated serial interface signa l timings name minimum typical maximu units description t1 5 ns fsdo/fscts hold time t2 5 ns fsdo/fscts setup time t3 5 ns fsdi hold time t4 10 ns fsdi setup time t5 10 ns fsclk low t6 10 ns fsclk high t7 20 ns fsclk period
copyright ? 201 2 future technology devi ces international limited 38 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.8.1 outgoing fast serial data to send fast serial data out of the ft2232h, the external device must drive the fsclk clock. if the ft2232h has data ready to send, it will drive fsdo output low to indicate the start bit. it will not do this if it is currently receiving data from the external device. this is illustrated in figure 4 . 14 . figure 4 . 14 fast opto - isolated serial interface output data notes : - 1. the first bit output (start bit) is always 0. 2. fsdo is always sent lsb first. 3. the last serial bit output is the source bit (srce). it indicates which channel the data has come from. a ?0? means that it has come from channel a, a ?1? means that it has co me from channel b. 4. if the target device is unable to accept the data when it detects the start bit, it should stop the fsclk until it can accept the data. 4.8.2 incoming fast serial data an external device is allowed to send data into the ft2232h if fscts is hig h. on receipt of a zero start bit on fsdi, the ft2232h will drop fscts on the next positive clock edge. the data from bits 0 to 7 are then clocked in (lsb first). the last bit (dest) determines where the data will be written to. the data can be sent to eit her channel a or to channel b. if dest= ?0?, the data is sent to channel a, (assuming channel a is enabled for fast serial mode, otherwise the data is sent to channel b). if dest= ?1? the data is sent to channel b, (assuming channel b is enabled for fast s erial mode, otherwise the data will go to channel a. (either channel a, channel b or both channels must be enabled as fast serial mode or the function is disabled). this is illustrated in figure 4 . 15 . figure 4 . 15 fast opto - isolated serial interface input data notes : - 1. the first bit input (start bit) is always 0. 2. fsdi is always received lsb first. 3. the last received serial bit is the destination bit (dest).i t indicates which channel the data should go to. a ?0? means that it should go to channel a, a ?1? means that it should go to channel b. 4. the target device should ensure that cts is high before it sends data. cts goes low after data bit 0 (d0) and stays low until the chip can accept more data. fsclk fsdo 0 d0 d1 d2 d3 d4 d5 d6 d7 srce start bit data bits - lsb first source bit fsclk fsdi 0 d0 d1 d2 d3 d4 d5 d6 d7 dest start bit data bits - lsb first destination bit fscts
copyright ? 201 2 future technology devi ces international limited 39 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.8.3 fast opto - isolated serial data interface example the following example, figure 4 . 16 , shows two agilent hcpl - 2430 (see the semiconductor section at www.agilent.com ) high speed opto - couplers used to optically isolate an external device which interfaced to usb using the ft2232h. in this example vcc5v is the usb vbus supply and vcce is the supply to the external device. care must be taken with the voltage used to power the photo - led?s. it must be the same voltage as that the ft2232h i/os are driving to, or the led?s may be permanently on. limiting resistors should be fitted in the lines that drive the diodes. the outputs of the opto - couplers are open - collector and require a pull - up resistor. figure 4 . 16 fast opto - isolated serial interface example ft 2232 h fsdi fsclk fsdo fscts vcc 5 v hcpl - 2430 vcce hcpl - 2430 1 k 1 k 1 k 1 k 470 r 470 r 470 r 470 r vcce cable di clk do cts vcc 5 v 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
copyright ? 201 2 future technology devi ces international limited 40 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.9 cpu - style fifo interface mode description cpu - style fifo interface mode is designed to allow a cpu to interface to usb via the ft2232h. this mode is enabled in the external eeprom. the interface is achieved using a chip select bit (cs#) and address bit (a0). when either channe l a or channel b are in cpu - style interface mode the i o signal lines are configured as given in table 3 . 10 . this mode uses a combination of cs# and a0 to determine the operation to be carried out. the following truth - table, table 4 . 7 , gives the decode values for particular operations. cs# a0 rd# wr # 1 x x x 0 0 read data pipe write data pipe 0 1 read status send immediate table 4 . 7 cpu - style fifo interface o peration select the status read is shown in table 4 . 8 data bit data status bit 0 1 data available (=rxf) bit 1 1 space available (=txe) bit 2 1 suspend bit 3 1 configured bit 4 x x bit 5 x x bit 6 x x bit 7 x x table 4 . 8 cpu - style fifo interface operation read status description note that bits 7 to 4 can be arbitrary values and that x= not used. the timing of reading and writing in this mode is shown in figure 4 . 17 and table 4 . 9 . figure 4 . 17 cpu - style fifo interface operation signal waveforms. cs# wr# rd# a0 valid valid valid valid t3 t1 t2 t4 t5 t6 t7 d7..0
copyright ? 201 2 future technology devi ces international limited 41 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 table 4 . 9 cpu - style fifo interface operation signal timing. an example of the cpu - style fifo interface connection is shown in figure 4 . 18 figure 4 . 18 cpu - style fifo interface example name minimum typical maximum units description t1 15 ns a0 / cs setup to wr# t2 15 ns data setup to wr# t3 20 ns wr# pulse width t4 5 ns a0/cs hold from wr# t5 5 ns data hold from wr# t6 15 ns a0/cs setup to rd# t7 15 50 ns data delay from rd# t8 5 ns a0/cs hold from rd# t9 0 30 ns data hold time from rd# d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 rd # si / wu cs # wr # a 0 ft 2232 h io 10 io 11 io 12 io 13 io 14 io 15 io 16 io 17 io 20 io 24 io 23 io 21 io 22 microcontroller i o p o r t 1 i o p o r t 2 ( optional ) pwren # io 25 ( optional ) channel a or b
copyright ? 201 2 future technology devi ces international limited 42 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.10 synchronous and asynchronous bit - bang interface mode description the ft2232h channel a or channel b can be configured as a bit - bang interface. there are tw o types of bit - bang modes: synchronous and asynchronous. asynchronous bit - bang mode asynchronous bit - bang mode is the same as bm - style bit - bang mode, exce pt that the internal rd# and wr # strobes (rdstb# and wrstb#) are now brought out of the device to al low external logic to be clocked by accesses to the bit - bang io bus. on either or both channels any data written to the device in the normal manner will be self clocked onto the data pins (those which have been configured as outputs). each pin can be indep endently set as an input or an output. the rate that the data is clocked out at is controlled by the baud rate generator. for the data to change there has to be new data written, and the baud rate clock has to tick. if no new data is written to the channel , the pins will hold the last value written. synchronous bit - bang mode the synchronous bit - bang mode will only update the output parallel port pins whenever data is sent from the usb interface to the parallel interface. when this is done, the wrstb# will a ctivate to indicate that the data has been read from the usb rx fifo buffer and written out on the pins. data can only be received from the parallel pins (to the usb tx fifo interface) when the parallel interface has been written to. with synchronous bit - bang mode data will only be sent out by the ft2232h if there is space in the ft2232h usb txfifo for data to be read from the parallel interface pins. this synchronous bit - bang mode will read the data bus parallel i/o pins first, before it transmits data fr om the usb rxfifo. it is therefore 1 byte behind the output, and so to read the inputs for the byte that you have just sent, another byte must be sent. for example : - (1) pins start at 0xff send 0x55,0xaa pins go to 0x55 and then to 0xaa data read = 0xff ,0x55 (2) pins start at 0xff send 0x55,0xaa,0xaa (repeat the last byte sent) pins go to 0x55 and then to 0xaa data read = 0xff,0x55,0xaa synchronous bit - bang mode differs from asynchronous bit - bang mode in that the device parallel output is only read when the parallel output is written to by the usb interface. this makes it easier for the controlling program to measure the response to a usb output stimulus as the data returned to the usb interface is synchronous to the output data. asynchronous bit - bang mo de is enabled using set bit bang mode driver command. a hex value of 1 will enable asynchronous bit - bang mode. synchronous bit - bang mode is enabled using set bit bang mode driver command. a hex value of 4 will enable synchronous bit - bang mode. see applica tion note an2232 - 02, bit mode functions for the ft2232 for more details and examples of using the bit - bang modes. an example of the synchronous bi - bang mode timing is shown in figure 4 . 19
copyright ? 201 2 future technology devi ces international limited 43 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 figure 4 . 19 synchronous bit - bang mode timing interface example table 4 . 10 synchronous bit - bang mode timing interface e xample timings wrstb# = this output indicates when new data has been written to the i/o pins from the host pc (via the usb interface) . rdstb# = this output rising edge indicates when data has been read from the i/o pins and sent to the host pc (via the usb interface) . the wrstb# goes active in t4. the wrstb# goes active when data is read from the usb rxfifo (i.e. sent from the pc). the rdstb# goes inactive when data is sampled from the pins and written to the usb txfifo (i.e. sent to the pc). the setup comm and to the ft2232h is used to setup the bit - mode. this command also contains a byte wide data mask to set the direction of each bit. the direction on each pin doesn?t change unless a new setup command is used to modify the direction. the wrstb# and rdstb# strobes are only a guide to what may be happening depending on the direction of the bus. for example if all pins are configured as inputs, it is still necessary to write to these pins in order to get the ft2232h to read those pins even though the data wri tten will never appear on the pins. signals and data - flow are illustrated in figure 4 . 20 figure 4 . 20 bit - bang mode dataflow il lustration diagram. w r s t b # r d s t b # name description t1 current pin state is read t2 rdstb# is set inactive and data on the paralle i/o pins is read and sent to the usb host. t3 rdstb# is set active again, and any pins that are output will change to their new data t4 1 clock cycle to allow for data setup t5 wrstb# goes active. this indicates that the host pc has written new data to the i/o parallel data pins t6 wrstb# goes inactive u s b r x f i f o / b u f f e r p a r a l l e l i / o d a t a p a r a l l e l i / o p i n s u s b w r s t b # r d s t b # u s b t x f i f o / b u f f e r
copyright ? 201 2 future technology devi ces international limited 44 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.11 rs232 uart mode led interface description when configured in uart mode the ft2232h has two io pins on each channel dedicated to controlling led status indicators, one for transmitted data the other for received data. when data is being transmitted / received the respective pins drive from tri - state to low in order to provide indication on the led?s of data transfer. a digital one - shot timer is used so that even a small percentage of data transfer is visible to the end user. figure 4 . 21 dual led uart configuration figure 4 . 21 shows a configuration using two individual led?s C one for transmitted data the other for received data. figu re 4 . 22 single led uart configuration in figu re 4 . 22 the transmit and receive led indicators are wire - or?ed together to give a single led indicator which i ndicates any transmit or receive data activity. note that the led?s are connected to the same supply as vccio. ft 2232 h txled # rxled # vccio 220 r 220 r tx rx ft 2232 h txled # rxled # vccio 220 r led
copyright ? 201 2 future technology devi ces international limited 45 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 4.12 send immediate / wake up (siwu # ) the siwu # function is available in the fifo modes and in bitbang mode. the send immediate portion is used t o flush data from the chip back to the pc. this can be used to get short packets of data back to the pc without waiting for the latency timer to expire. this mechanism should only be used when you have stopped sending data to the chip to avoid overrun. the data transfer is flagged to the usb host by the falling edge of the signal. figure 4. 23 : using siwu# when the pin is being used for a wake up function to wake up a sleeping pc a 20ms negative pulse on th is pin is required. when the pin is being used to flush the buffer (send immediate), a 250ns negative pulse on this pin is required. notes 1. when using remote wake - up, ensure the resistors are pulled - up in suspend. also ensure peripheral designs do not al low any current sink paths that may partially power the peripheral. 2. if remote wake - up is enabled, a peripheral is allowed to draw up to 2.5ma in suspend. if remote wake - up is disabled, the peripheral must draw no more than 500ua in suspend. 3. if a pull - do wn is enabled, the ft2232h will not wake up from suspend. c l k o u t w r # s i w u # d 7 - d 0
copyright ? 201 2 future technology devi ces international limited 46 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 ft2232h mode selection the 2 channels of the ft2232h reset to 2 asynchronous serial interfaces. following a reset the required mode of each channel is determined by the contents of the eeprom (pro grammed using mprog v3.4a or later). the eeprom contents determine if the 2 channels have been configured as ft232 asynchronous serial inter face, ft245 fifo interface, cpu - style fifo interface or fast serial interface. following a reset, the eeprom is re ad to determine which mode is configured. after device enumeration, an ft_setbitmode command (refer to d2xx_programmers_guide ) can be sent to the usb driver to switch the selected interface into the required mode C asynchronous bit - bang, synchronous bit - ba ng or mpsse. when in ft245 fifo mode, the ft_setbitmode command can be used to select either synchronous fifo ( ft_setbitmode = 0x40) or asynchronous fifo mode. (note that asynchronous fifo mode must be selected on both channels before selecting the synchro nous fifo mode. this means that an eeprom is needed to initially configure asynchronous fifo mode before software configures the synchronous fifo mode). when synchronous fifo mode selected, channel a uses all the memory resources of channel b. as such chan nel b is then not available. in this case the state of the channel b pins is determined when the configuration is switched to asynchronous fifo mode. if channel b had not been used for any data transfer before configuration of asynchronous fifo mode, then the channel b pins will remain in their default mode (d7:0=tri - stated but pulled high trough 75k resistor, tx e# =low, rxf# =high. rd# and wr # are inputs and should be pulled high). an mpsse command, set_data_bits can be used to configure the channel b pins as inputs before configuring channel a as synchronous fifo. this avoids the channel b pins driving against any interfaces (such as spi) which may have been configured previous to any switching of channel a to synchronous fifo mode. refer to http://www.ftdichip.com/documents/appnotes/an2232c - 01_mpsse_cmnd.pdf for the set_data_bits command and further information on the mpsse used in mcu host bus emulation mode. the mpsse can be configured directly using the d2xx commands. the d2xx_programmers_guide is available from the ftdi website at http://www.ftdichip.com/documents/programgu ides/d2xx_programmer?s_guide(ft_000071).pdf the application note an_108 C command processor for mpsse and mcu host bus emulation modes gives further explanation and examples for the mpsse. 4.12.1 do i need an eeprom? the following table table 4 . 11 summarises what modes are configurable using the eeprom or the application software. async serial uart async 245 fifo sync 245 fifo asyn c bit - bang sync bit - bang mpsse fast serial interface cpu - style fifo host bus em ulation eeprom configured yes yes yes yes yes application software configured yes yes yes yes yes table 4 . 11 configuration using eeprom and application software
copyright ? 201 2 future technology devi ces international limited 47 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 5 devices characteristics and ratings 5.1 absolute maximum ratings the absolute maximum ratings for the ft2232h devices are as follows. these are in accordance with the absolute maximum rating system (iec 60134). exceeding these values may cause permanent damage to the device. parameter value uni t storage temperature - 65c to 150c degrees c floor life (out of bag) at factory ambient (30c / 60% relative humidity) 168 hours (ipc/jedec j - std - 033a msl level 3 compliant)* hours ambient operating temperature (power applied) - 40c to 85c degrees c mttf ft2232hl tbd hours mttf ft2232hq tbd hours vcore supply voltage - 0.3 to +2.0 v vccio io voltage - 0.3 to +4.0 v dc input voltage C usbdp and usbdm - 0.5 to +3.63 v dc input voltage C high impedance bi - directionals (powered from vccio) - 0.3 to +5.8 v dc input voltage C all other inputs such as pwren#, suspend#, reset#, eecs, eeclk, eedata - 0.5 to + ( vccio +0.5) v dc output current C outputs 16 ma table 5 . 1 absolute maximum ratings * if device s are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of +125 c and baked for up to 17 hours .
copyright ? 201 2 future technology devi ces international limited 48 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 5.2 dc characteristics the i/o pins are +3.3v cells, which are +5v toler ant (except the usb phy pins). dc characteristics (ambient temperature = - 40c to +85c) parameter description minimum typical maximum units conditions vcore vcc core operating supply voltage 1.62 1.80 1.98 v vccio * vccio operating supply voltage 2.97 3 .30 3.63 v cells are 5v tolerant vregin vregin voltage regulator input 3.00 3.30 3.60 v vregout voltage regulator output 1.71 1.80 1.89 v ireg regulator current 150 ma vregin +3.3v icc1 core operating supply current --- 70 --- ma vcore = +1.8v norm al operation icc1r core reset supply current --- 5 --- ma vcore = +1.8v device in reset state icc1s core suspend supply current 500 a vcore = +1.8v usb suspend table 5 . 2 operating voltage and current (ex cept phy) *note: failure to connect all vccio pins will result in failure of the device.
copyright ? 201 2 future technology devi ces international limited 49 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 the i/o pins are +3.3v cells, which are +5v tolerant (except the usb phy pins). parameter description minimum typical maximum units conditions voh output voltage hi gh 2.40 3.14 v ioh = +/ - 2ma i/o drive strength* = 4ma 3.20 v i/o drive strength* = 8ma 3.22 v i/o drive strength* = 12ma 3.22 v i/o drive strength* = 16ma vol output voltage low 0.18 0.40 v iol = +/ - 2ma i/o drive strength* = 4ma 0.12 v i/o drive strength* = 8ma 0.08 v i/o drive strength* = 12ma 0.07 v i/o drive strength* = 16ma vil input low switching threshold - 0.80 v lvttl vih input high switching threshold 2.00 - v lvttl vt switching threshold 1.50 v lvttl vt - sc hmitt trigger negative going threshold voltage 0.80 1.10 - v vt+ schmitt trigger positive going threshold voltage 1.60 2.00 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vccio iin input leakage current 15 45 85 a vin = 0 ioz tri - state output leakage current +/ - 10 a vin = 5.5v or 0 table 5 . 3 i/o pin characteristics vccio = +3.3v (except usb phy pins) * the i/o drive strength and slow slew - rate a re configurable in the eeprom.
copyright ? 201 2 future technology devi ces international limited 50 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 dc characteristics (ambient temperature = - 40c to +85c) parameter description minimum typical maximum units conditions vphy, vpll phy operating supply voltage 3.0 3.3 3.6 v 3.3v i/o iccphy phy operating supply current -- - 30 60 ma high - speed operation at 480 mhz iccphy (susp) phy operating supply current --- 10 50 a usb suspend table 5 . 4 phy operating voltage and current parameter description minimum typical maximum units conditions voh output voltage high vcore - 0.2 v vol output voltage low 0.2 v vil input low switching threshold - 0.8 v vih input high switching threshold 2.0 - v table 5 . 5 phy i/o pin characteristics 5.3 esd tolerance e sd protection for ft2 232h io?s parameter reference minimum typical maximu m units human body model (hbm) jedec eia/ jesd22 - a114 - b, class 2 2kv kv machine mode (mm) jedec eia/ jesd22 - a115 - a, class b 200v v charge device model (cdm) jedec eia/ jesd22 - c101 - d, class - iii 500v v latch - up jesd78, trigger class - ii 200ma ma table 5 . 6 esd tolerance
copyright ? 201 2 future technology devi ces international limited 51 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 6 ft2232h configurations the following sections illustrate possible usb power configurations for the ft2232h. all usb power configurations illustrated apply to both package options f or the ft2232h device 6.1 usb bus powered configuration bus powered application example 1: bus powered configuration figure 6 . 1 bus powered configuration example 1 figure 6 . 1 illustrates the ft2232h in a typical usb bus powered design configuration. a usb bus powered device gets its power from the usb bus. in this application, the ft2232h requires that the vbus (usb +5v) is regulated down to +3.3v (using an ldo) to supply the vccio, vpll, vphy and vregin. vregin is the +3.3v input to the on chip +1.8v regulator. the output of the on chip ldo regulator (+1.8v) drives the ft2232h core supply (vcore). this requires a minimum of a 3.3uf filter capacitor. g n d 1 o s c i 2 o s c o 3 v p h y 4 g n d 5 r e f 6 d m 7 d p 8 v p l l 9 a g n d 1 0 g n d 1 1 v c o r e 1 2 t e s t 1 3 r e s e t # 1 4 g n d 1 5 a d b u s 0 1 6 1 7 1 8 1 9 v c c i o 2 0 2 1 2 2 2 3 2 4 g n d 2 5 2 6 2 7 2 8 2 9 3 0 v c c i o 3 1 3 2 3 3 3 4 g n d 3 5 s u s p e n d # 3 6 v c o r e 3 7 3 8 3 9 4 0 4 1 v c c i o 4 2 4 3 4 4 4 5 4 6 g n d 4 7 4 8 v r e g o u t 4 9 v r e g i n 5 0 g n d 5 1 5 2 5 3 5 4 v c c i o 5 6 5 5 5 7 5 8 5 9 p w r e n # 6 0 e e c l k 6 2 e e d a t a 6 1 e e c s 6 3 v c o r e 6 4 v i n v o u t g n d l d o + 3 . 3 v g n d v b u s 1 d - 2 d + 3 g n d 4 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f g n d g n d g n d g n d g n d 4 . 7 u f 4 . 7 u f g n d g n d + 1 . 8 v + 3 . 3 v + 1 . 8 v + 3 . 3 v 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f 1 0 0 n f + 1 . 8 v + 1 . 8 v + 1 . 8 v + 3 . 3 v + 3 . 3 v + 3 . 3 v + 3 . 3 v g n d g n d g n d g n d g n d g n d g n d + 3 . 3 v + 3 . 3 v 1 2 k 1 k g n d + 3 . 3 v c s 1 s c l 2 d 3 q 4 g n d 5 o r g 6 d u 7 v c c 8 9 3 c 4 6 g n d g n d g n d + 3 . 3 v + 3 . 3 v 2 . 2 k 1 0 k 1 0 k 1 0 k 1 3 1 2 m h z e e c l k e e d a t a g n d a d b u s 1 a d b u s 2 a d b u s 3 a d b u s 4 a d b u s 5 a d b u s 6 a d b u s 7 a c b u s 0 a c b u s 1 a c b u s 2 a c b u s 3 a c b u s 4 a c b u s 5 a c b u s 6 a c b u s 7 b d b u s 0 b d b u s 1 b d b u s 2 b d b u s 3 b d b u s 4 b d b u s 5 b d b u s 6 b d b u s 7 b c b u s 0 b c b u s 1 b c b u s 2 b c b u s 3 b c b u s 4 b c b u s 5 b c b u s 6 b c b u s 7 0 ? g n d 2 7 p f 2 7 p f 3 . 3 u f
copyright ? 201 2 future technology devi ces international limited 52 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 bus powered application example 2: bus powered configuration (with additional 1.8v ldo voltage regulator for vcore) figure 6 . 2 bus powered configuration example 2 figure 6 . 3 illustrates the ft2232h in a typical usb bus powered configuration similar to figure 6 . 1 . the difference here is that the +1.8v for the ft2232h core (vcore) has been regulated from the vbus as well as the +3.3v supply to the vpll, vphy, vccio and vregin. vbus 1 d - 2 d + 3 gnd 4 100 nf 100 nf gnd gnd 4 . 7 uf 4 . 7 uf gnd gnd + 1 . 8 v + 3 . 3 v 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf + 1 . 8 v + 1 . 8 v + 1 . 8 v + 3 . 3 v + 3 . 3 v + 3 . 3 v + 3 . 3 v gnd gnd gnd gnd gnd gnd gnd + 3 . 3 v + 3 . 3 v 12 k 1 k gnd + 3 . 3 v cs 1 scl 2 d 3 q 4 gnd 5 org 6 du 7 vcc 8 93 c 46 gnd gnd gnd + 3 . 3 v + 3 . 3 v 2 . 2 k 10 k 10 k 10 k 1 3 12 mhz eeclk eedata gnd vin vout gnd ldo + 1 . 8 v gnd + 1 . 8 v 100 nf gnd 100 nf gnd g n d 1 osci 2 osco 3 v p h y 4 g n d 5 ref 6 dm 7 dp 8 v p l l 9 a g n d 1 0 g n d 1 1 v c o r e 1 2 test 13 reset # 14 g n d 1 5 adbus 0 16 17 18 19 v c c i o 2 0 21 22 23 24 g n d 2 5 26 27 28 29 30 v c c i o 3 1 32 33 34 g n d 3 5 suspend # 36 v c o r e 3 7 38 39 40 41 v c c i o 4 2 43 44 45 46 g n d 4 7 48 vregout 49 vregin 50 g n d 5 1 52 53 54 v c c i o 5 6 55 57 58 59 pwren # 60 eeclk 62 eedata 61 eecs 63 v c o r e 6 4 adbus 1 adbus 2 adbus 3 adbus 4 adbus 5 adbus 6 adbus 7 acbus 0 acbus 1 acbus 2 acbus 3 acbus 4 acbus 5 acbus 6 acbus 7 bdbus 0 bdbus 1 bdbus 2 bdbus 3 bdbus 4 bdbus 5 bdbus 6 bdbus 7 bcbus 0 bcbus 1 bcbus 2 bcbus 3 bcbus 4 bcbus 5 bcbus 6 bcbus 7 0 ? gnd 27 pf 27 pf vin vout gnd ldo + 3 . 3 v gnd 100 nf 100 nf gnd gnd + 3 . 3 v
copyright ? 201 2 future technology devi ces international limited 53 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 6.2 usb self powered configuration self powered application example 1: self powered configuration figure 6 . 3 self powe red configuration example 1 figure 6 . 3 illustrates the ft2232h in a typical usb self powered configuration. a usb self powered device gets its power from its own power supply and does not draw current fro m the usb bus. in this example an external power supply is used. this external supply is regulated to +3.3v. note that in this set - up, the eeprom should be config ured for self - powered operation and the option suspend on dbus7 low selected in mprog. also this configuration uses the pin bcbus7, so this assumes that mpsse mode is not selected. vin vout gnd ldo + 3 . 3 v gnd vbus 1 d - 2 d + 3 gnd 4 100 nf 100 nf 3 . 3 uf 100 nf 100 nf gnd gnd gnd gnd gnd 4 . 7 uf 4 . 7 uf gnd gnd + 1 . 8 v + 3 . 3 v + 1 . 8 v + 3 . 3 v 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf + 1 . 8 v + 1 . 8 v + 1 . 8 v + 3 . 3 v + 3 . 3 v + 3 . 3 v + 3 . 3 v gnd gnd gnd gnd gnd gnd gnd + 3 . 3 v + 3 . 3 v 12 k 1 k gnd + 3 . 3 v cs 1 scl 2 d 3 q 4 gnd 5 org 6 du 7 vcc 8 93 c 46 gnd gnd gnd + 3 . 3 v + 3 . 3 v 2 . 2 k 10 k 10 k 10 k 1 3 12 mhz eeclk eedata gnd 1 2 ext . power sup p ly gnd g n d 1 osci 2 osco 3 v p h y 4 g n d 5 ref 6 dm 7 dp 8 v p l l 9 a g n d 1 0 g n d 1 1 v c o r e 1 2 test 13 reset # 14 g n d 1 5 adbus 0 16 17 18 19 v c c i o 2 0 21 22 23 24 g n d 2 5 26 27 28 29 30 v c c i o 3 1 32 33 34 g n d 3 5 suspend # 36 v c o r e 3 7 38 39 40 41 v c c i o 4 2 43 44 45 46 g n d 4 7 48 vregout 49 vregin 50 g n d 5 1 52 53 54 v c c i o 5 6 55 57 58 59 pwren # 60 eeclk 62 eedata 61 eecs 63 v c o r e 6 4 adbus 1 adbus 2 adbus 3 adbus 4 adbus 5 adbus 6 adbus 7 acbus 0 acbus 1 acbus 2 acbus 3 acbus 4 acbus 5 acbus 6 acbus 7 bdbus 0 bdbus 1 bdbus 2 bdbus 3 bdbus 4 bdbus 5 bdbus 6 bdbus 7 bcbus 0 bcbus 1 bcbus 2 bcbus 3 bcbus 4 bcbus 5 bcbus 6 bcbus 7 0 ? gnd 27 pf 27 pf vbus vbus gnd 10 k 4 . 7 k
copyright ? 201 2 future technology devi ces international limited 54 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 self powered application example 2: self powered configuration (with additional 1.8v ldo voltage regulator for vcore) figure 6 . 4 self powered configuration example 2 figure 6 . 4 illustrates the ft2232h in a typical usb self powered configuration similar to figure 6 . 3 . the difference here is that the +1.8v for the ft2232h core has been regulated from the external power supply. note that in this set - up, the eeprom should be configured for self - powered oper ation and the option suspend on dbus7 low selected in mprog. also this configuration uses the pin bcbus7, so this assumes that mpsse mode is not selected. vbus 1 d - 2 d + 3 gnd 100 nf 100 nf gnd gnd 4 . 7 uf 4 . 7 uf gnd gnd + 1 . 8 v + 3 . 3 v 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf 100 nf + 1 . 8 v + 1 . 8 v + 1 . 8 v + 3 . 3 v + 3 . 3 v + 3 . 3 v + 3 . 3 v gnd gnd gnd gnd gnd gnd gnd + 3 . 3 v + 3 . 3 v 12 k 1 k gnd + 3 . 3 v 27 pf cs 1 scl 2 d 3 q 4 gnd 5 org 6 du 7 vcc 8 93 c 46 gnd gnd gnd + 3 . 3 v + 3 . 3 v 2 . 2 k 10 k 10 k 10 k 1 3 12 mhz eeclk eedata gnd vin vout gnd ldo + 1 . 8 v gnd + 1 . 8 v 100 nf gnd 100 nf gnd 1 2 ext . power sup p ly gnd g n d 1 osci 2 osco 3 v p h y 4 g n d 5 ref 6 dm 7 dp 8 v p l l 9 a g n d 1 0 g n d 1 1 v c o r e 1 2 test 13 reset # 14 g n d 1 5 adbus 0 16 17 18 19 v c c i o 2 0 21 22 23 24 g n d 2 5 26 27 28 29 30 v c c i o 3 1 32 33 34 g n d 3 5 suspend # 36 v c o r e 3 7 38 39 40 41 v c c i o 4 2 43 44 45 46 g n d 4 7 48 vregout 49 vregin 50 g n d 5 1 52 53 54 v c c i o 5 6 55 57 58 59 pwren # 60 eeclk 62 eedata 61 eecs 63 v c o r e 6 4 adbus 1 adbus 2 adbus 3 adbus 4 adbus 5 adbus 6 adbus 7 acbus 0 acbus 1 acbus 2 acbus 3 acbus 4 acbus 5 acbus 6 acbus 7 bdbus 0 bdbus 1 bdbus 2 bdbus 3 bdbus 4 bdbus 5 bdbus 6 bdbus 7 bcbus 0 bcbus 1 bcbus 2 bcbus 3 bcbus 4 bcbus 5 bcbus 6 bcbus 7 0 ? gnd 27 pf vbus gnd 10 k 4 . 7 k vbus vin vout gnd ldo + 3 . 3 v gnd 100 nf 100 nf gnd gnd + 3 . 3 v
copyright ? 201 2 future technology devi ces international limited 55 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 6.3 oscillator configuration figure 6 . 5 recommended ft2232h crystal oscillator configuration. figure 6 . 5 illustrates how to connect the ft2232h with a 12mhz 0.003 % crystal. in this case loading capacitors should to be added between osci, osco and gnd as shown. a value of 27pf is shown as the capacitor in the exa mple C this will be good for many crystals but it is recommended to select the loading capacitor value based on the manufacturer?s recommendations wherever possible. it is recommended to use a parallel cut type crystal. it is also possible to use a 12 mhz oscillator with the ft2232h. in this case the output of the oscillator would drive osci, and osco should be left unconnected. the oscillator must have a cmos output drive capability. parameter description minimum typical maximum units conditions osci vi n input voltage 2.97 3.30 3.63 v fin input frequency 12 mhz +/ - 30ppm ji cycle to cycle jitter < 150 ps table 6 . 1 osci input characteristics osci osco 2 3 ft 2 232 h crystal 12 mhz 27 pf 27 pf
copyright ? 201 2 future technology devi ces international limited 56 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 7 eeprom configuration if an external eeprom is fitted (93l c46/56/66) it can be programmed over usb using mprog v3.4a or later. the eeprom must be 16 bits wide and capable or working at a vcc supply of +3.0 to +3.6 volts.
copyright ? 201 2 future technology devi ces international limited 57 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 8 package parameters the ft2232h is available in two different packages. the ft2232hl is the l qfp - 64 option and the ft2232hq is the qfn - 64 package option. the solder reflow profile for both packages is described in section 8.3 8.1 ft2232hq, qfn - 64 package dimensions figure 8 . 1 64 pin qfn package details notes f t d i y y w w - a x x x x x x x x x x x x f t 2 2 3 2 h q 1 6 4 i n d i c a t e s p i n # 1 ( l a s e r m a r k e d ) t o p v i e w 1 6 1 7 3 2 3 3 4 8 4 9 9 . 0 0 0 + / - 0 . 0 7 5 9 . 0 0 0 + / - 0 . 0 7 5 l i n e 1 C f t d i l o g o l i n e 2 C d a t e c o d e a n d r e v i s i o n l i n e 3 C w a f e r l o t n u m b e r l i n e 4 C f t d i p a r t n u m b e r
copyright ? 201 2 future technology devi ces international limited 58 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 1. all dimensions are in mm. 2. pin 1 id can be combination of dot and/or chamfer. 3. pin 1 id is not connected to the internal ground of the device. it is internally connect ed to the bottom side central solder pad, which is 4.35 x 4.35mm. 4. pin 1 id can be connected to system ground, but it is not recommended using this as a ground point for the device . 5. optional chamfer on corner leads. 8.2 ft2232hl, lqfp - 64 package dimensio ns ft di yyww - a xxxxxxxxxxxx ft 2232 hl 1 64 indicates pin # 1 ( laser marked ) top view 16 17 32 33 48 49 10 . 000 +/ - 0 . 1 1 0 . 0 0 0 + / - 0 . 1 line 1 C ftdi logo l ine 2 C date code and revision l ine 3 C wafer lot number l ine 4 C ftdi part number dimensions are body dimensions ( mm )
copyright ? 201 2 future technology devi ces international limited 59 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 figure 8 . 2 64 pin lqfp package details symbol min nom max d 11.8 12 12.2 d1 9.9 10 10.1 e 11.8 12 12.2 e1 9.9 10 10.1 b 0.17 0.22 0.27 c 0.09 0.2 b1 0.17 0.2 0.23 c1 0.09 0.16 e 0.5 bsc table 8 . 1 64 pin lqfp package details C dimensions (in mm) 64 17 1 16 32 33 48 49 d 1 e 1 d e 0 . 25 1 . 6 0 m a x 12 o +/ - 1 o 1 . 4 + / - 0 . 0 5 0 . 2 min 0 . 6 +/ - 0 . 15 1 . 0 0 . 05 min 0 . 15 max b c b 1 c 1 e
copyright ? 201 2 future technology devi ces international limited 60 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 8.3 solder reflow profile figure 8 . 3 64 pin lqfp and qfn reflow solder profile
copyright ? 201 2 future technology devi ces international limited 61 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 profile feature pb f ree solder process (green material) snpb eutectic and pb free (non green material) solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 120 seconds 100c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 secon ds peak temperature (t p ) 260c see table 8 . 3 time within 5c of actual peak temperature (t p ) 30 to 40 seconds 20 to 40 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25 c to peak temperature, t p 8 minutes max. 6 minutes max. table 8 . 2 reflow profile parameter values snpb eutectic and pb free (non green material) package thickness volume mm3 < 350 volume mm3 >=350 < 2.5 mm 235 +5/ - 0 deg c 220 +5/ - 0 deg c 2.5 mm 220 +5/ - 0 deg c 220 +5/ - 0 deg c pb free (green material) = 260 +5/ - 0 deg c table 8 . 3 package reflow peak temperature
copyright ? 201 2 future technology devi ces international limited 62 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 9 contact information head office C glasgow, uk future technology devi ces international limited unit 1, 2 seaward place, glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales1@ftdichip.com e - mail (support) support1@ftdichip.com e - mail (general enquiries) admin1@ftdichip.com web site url http://www.ftdichip.com web shop url http: //www.ftdichip.com branch office C taipei, taiwan future technology devices international limited (taiwan) 2f, no. 516, sec. 1, neihu road taipei 114 taiwan , r.o.c. tel: +886 (0) 2 8797 1330 fax: +886 (0) 2 8751 9737 e - mail (sales) asia.sales1@ftdichip.com e - mail (support) asia.support1@ftdichip.com e - mail (general enquiries) asia.admin1@ftdichip.com web site url http://www.ftdichip.com branch office C hillsboro, oregon, usa future technology devices international limited (usa) 7235 nw evergreen parkway, suite 600 hillsboro, or 97123 - 5803 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com web site url http://www.ftdichip.com branch office C shanghai, china future technology devices international limited (china) room 408, 317 xianxia road, changning distric t, shanghai, china tel: +86 (21) 62351596 fax: +86 (21) 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site url: http://www.ftdichip.com
copyright ? 201 2 future technology devi ces international limited 63 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 distributor and sales representatives please visit the sales network page of the ftdi web site for th e contact details of our distributor(s) and sales representative(s) in your country.
copyright ? 201 2 future technology devi ces international limited 64 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 appendix a C list of figures and tables list of tables table 3.1 power and ground ................................ ................................ ................................ ........ 10 table 3.2 common function pins ................................ ................................ ................................ .. 11 table 3.3 eeprom interface group ................................ ................................ ............................... 11 table 3.4 channel a an d channel b rs232 configured pin descriptions ................................ ............. 12 table 3.5 channel a ft245 style synchronous fifo configured pin descriptions ................................ 13 table 3.6 channel a and channel b ft245 style asynchronous fifo configured pin descriptions .......... 14 table 3.7 channel a and channel b synchronous or asynchronous bit - bang configured pin descriptio ns ................................ ................................ ................................ ............................. 15 table 3.8 channel a and channel b mpsse configured pin descriptions ................................ .. 17 table 3.9 channel b fast serial interface configure d pin descriptions ................................ .... 17 table 3.10 channel a and channel b cpu - style fifo interface configured pin descriptions ... 18 table 3.11 chan nel a and channel b host bus emulation interface configured pin descriptions ................................ ................................ ................................ ................................ ................ 19 table 4.1 ft245 synchronous fifo interface signal timings ................................ ............................ 28 table 4.2 asynchronous fifo timings (based on standard drive level outputs) ...................... 30 table 4.3 mpsse signal timings ................................ ................................ ................................ ... 31 ta ble 4.4 mcu host bus emulation mode signal timings C write cycle ................................ ............... 34 table 4.5 mcu host bus emulation mode signal timings C read cycle ................................ ................. 35 table 4.6 fast opto - isolated serial interface signal timings ................................ ............................ 37 table 4.7 cpu - style fifo interface operation select ................................ .............................. 40 t able 4.8 cpu - style fifo interface operation read status description ................................ .. 40 table 4.9 cpu - style fifo interface operation signal timing. ................................ .................. 41 table 4.10 synchronous bit - bang mode timing interface example timings ................................ ........ 43 table 4.11 configuration using eeprom and application software ................................ ......... 46 table 5.1 absolute maximum ratings ................................ ................................ ............................ 47 table 5.2 operating voltage and current (except phy) ................................ ................................ .... 48 table 5.3 i/o pin characteristics vccio = +3.3v (except usb phy pins) ................................ ........... 49 table 5.4 phy operating voltage and current ................................ ................................ ................. 50 table 5.5 phy i/o pin cha racteristics ................................ ................................ ............................ 50 table 5.6 esd tolerance ................................ ................................ ................................ .............. 50 table 6.1 osci input characteristics ................................ ................................ ............................. 55 table 8.1 64 pin lqfp package details C dimensions (in mm) ................................ ........................... 59 table 8.2 reflow profile parameter values ................................ ................................ ..................... 61 ta ble 8.3 package reflow peak temperature ................................ ................................ .................. 61 list of figures figure 2.1 ft2232h block diagram ................................ ................................ ................................ . 5 figure 3.1 ft2232h schematic symbol ................................ ................................ ...................... 8
copyright ? 201 2 future technology devi ces international limited 65 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 figure 4.1 rs232 configuration ................................ ................................ ................................ .... 22 figure 4.2 dual rs422 configuration ................................ ................................ ............................. 23 figure 4.3 dual rs485 configuration ................................ ................................ ............................. 25 figure 4.4 ft245 synchronous fifo interface signal waveforms ................................ ...................... 27 figure 4.5 ft245 asynchronous fifo interface read signal waveforms ................................ ............ 29 figure 4.6 ft245 asynchronous fifo interface write signal waveforms ................................ .......... 29 figure 4.7 mpsse signal waveforms ................................ ................................ ............................. 31 figure 4.8 adaptive clocking interconnect ................................ ................................ ..................... 32 figure 4.9 : adaptive clocking waveform. ................................ ................................ ....................... 32 figure 4.10 mcu host bus emulation mode signal waveforms C write cycle ............................ 34 figure 4.11 mcu host bus emulation mode signal waveforms C read cycle ............................. 35 figure 4.12 mcu host emulation example using a canbus controller ................................ ................ 36 figure 4.13 fast opto - isolated serial interface signal waveforms ................................ .................... 37 figure 4.14 fast opto - isolated serial interface output data ................................ ............................ 38 figure 4.15 fast opto - isolated serial interface input data ................................ ............................... 38 figure 4.16 fast opto - isolated serial interface example ................................ ................................ .. 39 figure 4.17 cpu - style fifo interface operation signal waveforms. ................................ ....... 40 figure 4.18 cpu - style fifo interface example ................................ ................................ ............... 41 figure 4.19 synchronous bit - bang mode timing interface example ................................ ................... 43 figure 4.20 bit - bang mode dataflow illustration diagram. ................................ ...................... 43 figure 4.21 dual led uart configuration ................................ ................................ ................ 44 figure 4.22 single led uart configuration ................................ ................................ ............. 44 figure 4.23: using siwu# ................................ ................................ ................................ ....... 45 figure 6.1 bus powered con figuration example 1 ................................ ................................ ............ 51 figure 6.2 bus powered configuration example 2 ................................ ................................ ............ 52 figure 6.3 self powered configuration example 1 ................................ ................................ ........... 53 figure 6.4 self powered configuration example 2 ................................ ................................ ........... 54 figure 6.5 recommended ft2232h crystal oscillator configuration. ................................ ................. 55 figure 8.1 64 pin qfn package details ................................ ................................ .......................... 57 figure 8.2 64 pin lqfp package details ................................ ................................ ......................... 59 figure 8.3 64 pin lqfp and qfn reflow solder profile ................................ ................................ ..... 60
copyright ? 201 2 future technology devi ces international limited 66 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 appendix b C revision history document title: dual high speed usb to multipurpose uart/fifo ic ft2232h document reference no.: ft_000061 clearance no.: ftdi#77 product page: http://www.ftdichip.com/ftproducts.htm document feedback: send feedback revision history version draft initial datasheet created october 2008 version preliminary preliminary datasheet released 23 rd october 2008 version 1.00 datasheet released 4 th november 2008 version 1.10 qfn package updated november 2008 version 2.00 various updates january 2009 version 2.01 corrections made to table 3.6, 3.7, table on page 8. february 2009 changed description of wrstrb# and rdstrb# added note that hbe mode only operates at 60mhz version 2.02 corrections made to tray qfn 160 changed to 260 march 2009 co rrection made to 3.4.2, falling changed to rising version 2.03 correction s made to txled and rxled pin connections 1 9 th may 2009 corrected signals in figure 4.16. corrected signal names in fig 2.1 added reference to an_108, an_109, an_110, an_111 and an_113. version 2.04 added paragraph on latency timer to section 4.1 3 rd june 2009 version 2.05 corrected figures 6.2, 6.3 an 6.4 C miss ing regulators and better way 17 th june 2009 of holding self powered designs in reset if not conne cted to usb. corrected max dc inputs on dc input voltage C all other inputs pins from vcore+0.5v to vccio+0.5v version 2.06 added explanation of siwu (4.12) 21 st sept 2009 added explanation of mpsse adaptive clocking (4.6.1) . corrected 12 mhz crystal specification. added # to txled, rxled on table 3.4. corrected tx_led and rx_led connections on fig 4.1 version 2.07 edited table 3.11, references an2232l - 1 to an_108 12 march 2010 updated and formatted contact information. cor rected toc. version 2.08 added tid number ( section 1.3) 24 th may 2010 added esd specification s version 2.09 corrected ?wr? to ?wr#? throughtout the datasheet 2 nd sept 2010 edited table 4.1 (t8 and t13 comments ) edited section 4.7.1 and 4.7 .2 section 4.12, added clarifications about wake up
copyright ? 201 2 future technology devi ces international limited 67 document no.: ft_000061 ft2232h dual high speed usb to multipurpose uart/fifo ic version 2.21 clearance no.: ftdi#77 clarified unsupported baud rates of 7,9,10 and 11 mbaud. version 2.10 updated section 4.5, ft245 asynchronous fifo 22 nd nov 2010 interface timing diagram. edited section 4.3.2, 4.3.3, figur e 4.2 and 4.3. version 2.11 edited section 4.7. from bit a18 to a8 edited table 3.4 pin 29 and 30 description 07 th march 2012 added feedback links version 2.20 updated 245 fifo asynchronous timing table 4.2, 0 9 th april 2012 figure 4.5 a nd 4.6 version 2.2 1 u pdate performance of ft245 sync fifo mode 21 st june 2012 updated table 4. 1 , siwu# timing updated

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